Low-cost fault-tolerant microprocessing system for control and educational applications

Research output: Contribution to book or proceedingConference articlepeer-review

Abstract

In this paper, the design and implementation of a low cost, self-testing, fault-tolerant microprocessor system is presented. The system was implemented using an architecture based on the dynamic redundancy technique for the hardware, and supported by the application of software and time redundancy techniques. The final system that was obtained is highly reliable and can be used for control applications where reliable continuous execution is paramount, and the cost and power consumption is important.

Original languageEnglish
Title of host publicationProceedings of the IASTED International Conference on Circuits, Signals, and Systems
EditorsM.H. Rashid
Pages102-107
Number of pages6
StatePublished - 2004
EventProceedings of the IASTED International Conference on Circuits, Signals, and Systems - Clearwater Beach, FL, United States
Duration: Nov 28 2004Dec 1 2004

Publication series

NameProceedings of the IASTED International Conference on Circuits, Signals, and Systems

Conference

ConferenceProceedings of the IASTED International Conference on Circuits, Signals, and Systems
Country/TerritoryUnited States
CityClearwater Beach, FL
Period11/28/0412/1/04

Scopus Subject Areas

  • General Engineering

Keywords

  • Dynamic-Redundant
  • Fault-Tolerant
  • Low-Cost
  • Microprocessor

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